Prototron Soldermask

Keep them on the Inside

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By Mark Thompson | Published on: April 01, 2014

In this month's post I will be talking about some of the reasons both Fabricators and Customers may benefit by keeping any Impedance controlled lines on the internal layers.

EMI concerns. If any Impedance controlled lines can be kept to internal layers the outer layers can have additional shielding by adding additional copper pour. This creates a shield or a “can” to minimize emissions. Hopefully any small transmission lines that must be on the surface layers can be kept to less than .3 to .5 in length and at this point are most likely not impedance concerns. For those traces on the surface layer that must exist, the addition of copper pour close to the intended trace can also help to keep the sizes down.

See example below of how the addition of poured copper inducing co-planar coupling on the surface layers keeps the trace sizes down.

Fig-1 (Click Image to see Larger Version)

Fig-2 (Click Image to see Larger Version)

Surface impedances require wider line sizes than those on inner layers as they only have reference plane on one side. It is certainly true that dielectric distance between the intended Impedance line(s) and the reference plane can be reduced in an effort to keep these line sizes down. There are at least two potentially undesirable effects on the PCB when using thin dielectrics for a micro-strip ref plane below .004 in thickness.

Many times in order to keep a single-ended line size .005 or below on a surface these days the Fabricator must use a .004 mil dielectric distance or LESS to the reference plane. Most times this means a single ply of prepreg material. Depending upon the configuration of the reference plane itself, this reduced dielectric distance can result in things like high resistance shorts. Certainly on a board with a buried plate up, a single ply construction of .003 or less would not be wise; the additional plating acts as a cookie cutter, slicing through the single ply sometimes resulting in shorting. In addition, from a thermal cycling reliability standpoint, multiple plies of prepreg are better.

And finally, internal layers are generally printed and etched so there are no plating variances that can occur like they can on exterior layers. Because of this, tighter tolerances can be achieved. Another benefit of keeping Impedance signals on interior layers.

Let’s go back in time a little before we routinely used dielectrics less than .004 to a ref plane from a Surface layer…

When the 50 ohm line sizes and 100 ohm differential pairs were using an approximate dielectric distance of .005-.006 to the ref plane .008 lines got 50 ohms rather well as did the .005 lines with .005 spaces for 100 ohms. Now that the exterior line sizes are down around .0045-.005 the dielectric needs to be thinner to accommodate the 50 ohm structures. This means if the outer layer impedance lines for both 50 ohms and 100 ohms differential pairs were left at .005 /.005, the Differential pairs would have to be resized to around .003 lines with .007 spaces for 100 ohms with the thinner dielectric. Not a problem unless the power was calculated for the wider tracks! The best solution would be to keep all impedance signals on the inner layers.

But that not being an option, a solution we have seen to this is to have the .005 lines with .005 space diff pairs reference the third layer down in the stack (create a pass through of non metal on the layer 2 plane that is used for the 50 ohm SE transmission lines and add metal as ref plane on layer 3 for the .005 and .005 diff pairs). At approximately .007 -.008 dielectric distance .005 lines with .005 spaces get approximately 100.72 ohms for 100 on standard fr-406 type materials…

These types of solutions are becoming more and more frequent, but at the risk of making an electrical patchwork of varying emissions on the board!

Again, better yet if all impedances can be kept internally, there are fewer opportunities for impedance mismatches than there are with both internal and external impedances of the same value/threshold. An example of this would be that depending upon the layer count vs. layer orientation (location of signals vs. plane layers). The impedance lines for an external trace of one value most likely will have a different size than those for the same value on an internal layer and therefore performs differently.

Also, couple that with the fact internal signals generally do not require an additional plate up and therefore fabrication variation is reduced. The bottom line is that many designs, although electrically they may be a work of art, may not be well suited for fabrication. As always, I would say ultimately for the most reliable product consult your fabricator for specifics about dielectrics and effective dielectric constants prior to layout to reduce risks.


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