Prototron Soldermask

Signal Routing for Controlled Impedance

Bookmark and Share

By Mark Thompson | Published on: June 10, 2019

In This month’s Column we will be talking once again about Controlled Impedance structures both from the layout side and the simulation side. I will attempt to break them down into the sub categories of what model they represent and the important things to remember when using the various models. I will also be asking questions like, “What are the reasons why a fabricator would ask for a larger Impedance tolerance” and “Where does the fabricator draw the line for controlling various structures?” then Finally I will break down into 10 Do’s and Don’ts of signal routing.

Let’s start with Single ended structures both Co-planar and in “free space” (not coupled to any adjacent copper pour)

Some General rules of thumb:

For external single ended structures starting on Quarter or half ounce copper the trace width is typically approximately twice the dielectric needed between the Impedance signal and its reference plane.

Example: a 4.25 mil trace needs about a .0026-.0028 dielectric to reference plane for 50 ohms on half-ounce stating copper (One and half ounce after plate) The “3X Rule”

Keep the copper pour that resides on the impedance layer a minimum of 3 x whatever the chosen trace width for impedance is to ensure no unwanted co-planar coupling occurs. At larger trace widths upwards of .012 this distance can be as little as 2 x the trace width.

Differential Pairs:

Be sure you match the lengths of each half of the differential pair Make sure the same space is maintained throughout the run. (With the exception of neck down areas at the terminations) Be careful when terminating differential pairs that you do not create same net space violations where smaller traces (neck –downs) terminate. See example Fig-1 below.

Fig-1
Fig-1 (Click Image to see Larger Version)

Question: Why is this a problem?

Answer: if the same net space violation is LESS than the fabricators specified min space value and the fabricator is not aware these neck –down areas are part of larger /longer differential pairs they may “fill” the space violation...

And why is this a problem? If a fabricator “fills” in the same net space violation we have just changed the LENGTH of the differential pair!

Having said that a fabricator will not solve for the small neck –down sections, only the larger longer run of the same diff pair. This is true of SE structures as well. Really anything less than about .3 in length cannot be controlled to any great degree.

The same is true for surface single ended or differential pairs that have the vast majority of the run on one layer and only pickup the diff pair on the opposing side in very short lengths.

What are some reasons a fabricator may ask for a wider impedance tolerance?

  1. Lines less than. 1mm. Here many times a fabricator asks for +/-15% not because they may think they are not going to hit the number, remembering 10% of a .1mm trace is 4/10ths of a mil (less than half a mil!) hence the reason many shops ask for 15% for traces .004 and below.

  2. Additionally the fabricator may ask for 15% due to Less than predictable surface finishes- Let’s say the part has either epoxy or silver-epoxy filled vias and the fabricator has to use an outsource. The epoxy or silver –fill process itself requires that the material be pushed into the holes under pressure. After cure, they typically “planarize” (basically grind down the surface so it is flat) herein lies the rub. If the planarization process is not perfect there can be quarter to half a mil difference end to end on the surface topography making it more difficult to properly predict impedances.

OK let’s get into the 10 Do’s and Don’ts...

  1. Do ...Consult with your chosen fabricator regarding any controlled impedances at the earliest possible convenience.
    Don’ t ....assume that specifying dielectric only will meet your impedance requirements.

  2. Do....make sure your diff pairs have the same space throughout the run and are of matched length.
    Don’t....assume the ODD mode impedance is half the differential pair value.

  3. Do ...keep copper 3 x the trace width away from the impedance trace if no co-planar coupling is wanted.
    Don’t...vary the ground sep distance on the same layer. Keep all the ground separation distances the same on a given layer for all co-planar impedances.

  4. Do... make sure all structures have a proper reference plane.
    Don’t...place differential pairs over large splits on a plane layer.

  5. Do... remember the Dk gets lower as frequency gets higher.
    Don’t... assume all shops know this.

  6. Do...stick to calling out the desired material by its 4101/#
    Don’t.... assume all materials are the same.

  7. Do...add any bumps in differential pairs in an effort to match lengths somewhere away from the terminations.
    Don’t... wrap around a termination point creating same net spacing violations.

  8. Do....terminate traces in the center of the pad.
    Don’t.... terminate traces at the edge of the pad or device.

  9. Do... consult your chosen fabricator for minimum routing gaps for the desired copper weight.
    Don’t....rely on data sheets alone for proper Dk, Df info at a specific speed.

  10. Do....make sure what you have specified on the drawing for impedance trace widths actually exist.
    Don’t....callout Impedances solely by their net names.

Contact

Redmond Facility
15225 NE 95th Street
Redmond, WA 98052

Toll: 888.847.7686
Phone: 425.823.7000
Fax: 425.869.2515
email: Info@Prototron.com

Tucson Facility
3760 E. 43rd Place
Tucson, AZ 85713

Toll: 800.279.5572
Phone: 520.745.8515
Fax: 520.747.8334
email: Info@PrototronSW.com

Newsletter Signup

Sign up to stay in touch!

Sign-up