Prototron Soldermask

Unique Reference Plane Scenarios for Multiple Impedances

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By Mark Thompson | Published on: September 16, 2013

In this post I will talk about the use of unique reference plane scenarios for multiple impedances. What benefits they may have versus any drawbacks they may have.

As a fabricator, often we see customers using different reference planes for signals that exist on the same layer. An example of this would be some traces such as surface timing traces that may reference the next underlying layer in the stack up as a ground layer; these traces may be fairly small. In other sections of the same outer layer a larger trace may reference a plane buried somewhere deeper in the stack up such as a layer 3. The obvious benefit of this being that unused board real estate on internal signal layers can now have small patches of ground ref plane added to achieve multiple impedances.

How is this done?

In the case of the larger trace or traces, if in the setup for differential pairs for certain devices the ground layer 2 has a “pass through“ section below the intended impedance traces on the surface to allow the metal on layer 3 - or some other plane or signal plane layer buried deep in the stack up - to act as reference plane for the surface feature. Remembering that the further dielectric distance from the ground reference plane to the surface trace the wider the surface trace needs to be. Many times we see customers take this to an extreme and have all layers referencing all other layers in a jumble of multiple used reference planes. This can again be set up for crosstalk and other resonance issues if the part placement and proximities are not carefully calculated by the engineer prior to trace layout.


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